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The paper surveys practical challenges and solutions for processing-in-memory (PIM), focusing on identifying real‑world workloads that benefit from PIM, developing programming mode…

Publications (64)

Accelerating Generalized Linear Models with MLWeaving: A One-Size-Fits-All System for Any-precision Learning (Technical Report)

Banshee: Bandwidth-Efficient DRAM Caching Via Software/Hardware Cooperation

Tiered-Latency DRAM (TL-DRAM)

LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures

RowHammer: Reliability Analysis and Security Implications

A Workload and Programming Ease Driven Perspective of Processing-in-Memory

The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser

Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery

GRIM-filter: fast seed filtering in read mapping using emerging memory technologies

Recent Advances in DRAM and Flash Memory Architectures

SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators

ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms

Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory

The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity

Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming

Improving DRAM Performance by Parallelizing Refreshes with Accesses

Adaptive-Latency DRAM (AL-DRAM)

Improving Multi-Application Concurrency Support Within the GPU Memory System

Evaluating Row Buffer Locality in Future Non-Volatile Main Memories

Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions

Mosaic: An Application-Transparent Hardware-Software Cooperative Memory Manager for GPUs

Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface

Focus: Querying Large Video Datasets with Low Latency and Low Cost

Read Disturb Errors in MLC NAND Flash Memory

What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study

RowHammer: A Retrospective

Recent Advances in Overcoming Bottlenecks in Memory Systems and Managing Memory Resources in GPU Systems

RowHammer and Beyond

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins

Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid-State Drives

Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems

Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

MAGNET: Understanding and Improving the Accuracy of Genome Pre-Alignment Filtering

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

Decoupling GPU Programming Models from Resource Management for Enhanced Programming Ease, Portability, and Performance

A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps

Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost

A Memory Controller with Row Buffer Locality Awareness for Hybrid Memory Systems

Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses

Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing

Processing Data Where It Makes Sense: Enabling In-Memory Computation

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure

Zorua: Enhancing Programming Ease, Portability, and Performance in GPUs by Decoupling Programming Models from Resource Management

Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms

Optimal Seed Solver: Optimizing Seed Selection in Read Mapping

Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism

Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions

Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips

Enabling Practical Processing in and near Memory for Data-Intensive Computing

The Processing Using Memory Paradigm:In-DRAM Bulk Copy, Initialization, Bitwise AND and OR

RowClone: Accelerating Data Movement and Initialization Using DRAM

High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems

Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance

Heterogeneous-Reliability Memory: Exploiting Application-Level Memory Error Tolerance

Using ECC DRAM to Adaptively Increase Memory Capacity

LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency

Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism

Techniques for Efficiently Handling Power Surges in Fuel Cell Powered Data Centers: Modeling, Analysis, Results

An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories